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    • 专利摘要:
    A compound semiconductor substrate (Z) according to the present invention includes a compound semiconductor layer (3) formed on a main surface of a base substrate (1) over a start layer (2), wherein the base substrate (1) is formed of a sintered body, the start layer (3). 2) is formed of a single crystal, the compound semiconductor layer (3) includes a structure having a buffer layer (4) and an active layer (5) sequentially grown on the start layer (2), a thermal expansion coefficient of the sintered body O , 7 times or more and 1.4 times or less to an average thermal expansion coefficient of the entire compound semiconductor layer (3), and a FWHM of an X-ray diffraction peak of the buffer layer (4) obtained by an X-ray diffraction rocking curve measurement , 800 arcsec or less.
    公开号:BE1023890B1
    申请号:E20165760
    申请日:2016-10-10
    公开日:2017-09-06
    发明作者:Yoshihisa Abe；Kenichi Eriguchi；Noriko Omori；Hiroshi Oishi；Jun Komiyama
    申请人:Coors Tek Kk；
    IPC主号:
    专利说明:

    Compound semiconductor substrate
    Background of the invention
    THE iNVENTION field
    The present invention relates to a
    Compound semiconductor substrate.
    Description of the Related Art
    In manufacturing a compound semiconductor substrate by laminating compound semiconductor layers on a base substrate, a base substrate having a crystal plane according to the crystal orientation of the compound semiconductor layer to be formed on a main surface is used, and examples of the base substrate may include a silicon (Si) single crystal substrate or a sapphire single crystal substrate.
    In recent years, there is an increased demand for a compound semiconductor substrate having a large diameter or a thicker compound semiconductor layer. However, a warpage is caused when compound semiconductors are stacked on a single crystal substrate when the single crystal substrate has a larger diameter. Moreover, it is required that the single crystal substrate be processed in consideration of the plane orientation or the robustness due to the quality of the material, so that the formation thereof is limited. The cost of the single crystal substrate itself, particularly a sapphire substrate or a SiC substrate, is also high. It is therefore difficult to sufficiently satisfy these requirements as long as a single crystal substrate is used as a base substrate.
    It is therefore re-examined to use a sintered body material as a base substrate, which can be easily increased in diameter and is relatively inexpensive. JP 2006-315951 A discloses a technology for a thin film substrate obtained by forming a thin film consisting essentially of at least one selected from gallium nitride, indium nitride and aluminum nitride on a sintered body consisting essentially of a ceramic material wherein the thin film is obtained by forming a single crystal thin film on at least one selected from an amorphous thin film, a polycrystalline thin film and an oriented polycrystalline thin film, or wherein the thin film is obtained by forming a single crystal thin film on a single crystal thin film. Thin film and the crystallinity of the single crystal thin film formed on the other single crystal thin film is equal to or better than the crystallinity of the other single crystal thin film. WO 2012/043474 A1 discloses a polycrystalline aluminum nitride substrate for a GaN-based semiconductor crystal wax which comprises an auxiliary component to the
    Contains sintering of 1 to 10 mass%, has a thermal conductivity of 150W / m × K or more, and has no recess with a maximum diameter greater than 200μπι on the substrate surface as a substrate material for the grain growth of a GaN-based semiconductor. JP 2007-112633 A discloses a nitride semiconductor wafer having a substrate made of a polycrystalline aluminum nitride having an orientation and a plurality of steps formed on the main surface, and a single-crystal nitride semiconductor layer formed on the main surface of the substrate , and a nitride semiconductor element having an electrode formed on the nitride semiconductor layer for the purpose of providing a nitride semiconductor wafer and a nitride semiconductor element having excellent crystallinity while using a polycrystalline AlN substrate. JP 2013-258373 A discloses a method for producing a bonding substrate, which includes a step of preparing a sintered substrate having an average particle size of 0, 1 μτη or more and 30 μιη or less, and a step of bonding the sintered substrate with one
    Semiconductor crystal substrate by interposing a connection layer therebetween, and a step of forming a connection substrate in which a semiconductor crystal layer is bonded on the sintered substrate by inserting the connection layer by separating a part of the semiconductor crystal layer from the semiconductor crystal substrate. JP 5755390 B1 and JP 5756888 B2 disclose a technology in which a bonding substrate obtained by bonding a single crystal silicon donor substrate on a processing substrate of a polycrystalline material can be applied to a power device using a compound semiconductor.
    It would be advantageous in terms of cost to form a single crystal layer directly on a polycrystalline surface, but it is practically difficult to form a highly crystalline semiconductor layer on a polycrystalline surface by the technologies described in JP 2006-315951 A and WO 2012/043474 A1.
    Moreover, for example, in JP 2007-112633 A, it is disclosed that the c-axis is nearly parallel to the growth direction and further the a-axis or m-axis is nearly parallel or perpendicular to the extension direction of the step, and a single-crystal nitride semiconductor layer can be grown on a polycrystalline AlN substrate when a plurality of steps having a height of, for example, about several nanometers are formed on the surface of a polycrystalline AlN substrate so as to be substantially parallel to each other and a nitride semiconductor thereon is grown, so that a single crystal layer can be formed directly on a polycrystalline surface.
    However, it is laborious to form uniform and equal steps on the order of nanometers over the whole of a main surface of a substrate having a large size, and there is a fear that the steps are not uniform due to the presence of grain boundaries and voids on the polycrystalline substrate surface ,
    In the method according to JP 2013-258373 A, in which a semiconductor crystal layer is prepared beforehand and bonded to a polycrystalline substrate through a bonding layer and a part of the semiconductor crystal layer is separated, a substantial thickness is required in the bonding step or the separation step, however Cost of production, if the material for the semiconductor crystal layer, which is prepared in advance, are significant. In this case, moreover, it is difficult to produce a stacked structure of semiconductor crystal layers having different compositions, and the degree of freedom in formation as a semiconductor device is limited.
    The inventions described in JP 5755390 Bl and JP 5756888 B2 relate to a composite substrate obtained by bonding a single crystal body on a main surface of a polycrystalline body. It has also been attempted to manufacture a plurality of compound semiconductor substrates by stacking a compound semiconductor layer on a composite substrate by the same method of stacking a compound semiconductor layer on a single crystal substrate as in the prior art.
    However, it is expected that the application of the structure of a compound semiconductor layer of the prior art on the composite substrate will provide an excellent effect equal to or higher than in the case of coating a compound semiconductor layer on a single crystal substrate. However, it is not sufficiently clear which structure of a compound semiconductor and a composite substrate is a preferable shape.
    Summary of the invention
    In view of the above situation, an object of the present invention is to provide a compound semiconductor substrate having a sintered body as a base substrate, and which is suitable for producing a compound semiconductor element having better characteristics.
    A compound semiconductor substrate according to the present invention comprises a compound semiconductor layer formed on a main surface of a base substrate over a start layer, wherein the base substrate is formed of a sintered body, the start layer is formed of a single crystal, the compound semiconductor layer has a structure in which a buffer Layer and an active layer are sequentially grown on the starting layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less as an average thermal expansion coefficient of the entire compound semiconductor layer, and a * FWMH of an X-ray diffraction peak of the buffer Layer is 800 arcsec or less. (* FWHM: full width at half maximum)
    By such a configuration, a compound semiconductor substrate having better properties than those of the prior art can be obtained. In particular, the compound semiconductor substrate can have an excellent effect of suppressing warpage and cracking and the breakdown voltage characteristic while maintaining a low resistance value.
    In the compound semiconductor substrate according to the present invention, moreover, it is preferable that a layer thickness of the compound semiconductor layer is 7μτη or more and 15μπι or less.
    By such a configuration, the
    Breakdown voltage characteristic in a longitudinal direction of the compound semiconductor substrate can be sufficiently ensured and the electrical properties of the active layer can be improved.
    Examples of the configuration of the compound semiconductor substrate according to the present invention may here include a form in which the active layer is one obtained by forming an electron supply layer on an electron passage layer. In this case, it is preferable that a spacer layer is further provided between the electron passage layer and the electron supply layer.
    A specific example of the above-explained shape is moreover a shape in which the base substrate is one
    Aluminum nitride (AIN) sintered body, the starting layer is a silicon (Si) single crystal produced by the Czochralski (CZ) method or the floating zone (FZ) method, wherein the compound semiconductor is a gallium-based nitride manufactured is by a gas phase growth method, and the FWHM of the GaN (002) and GaN (100) X-ray diffraction peaks of the buffer layer are 500 arcsec or less, respectively.
    According to the present invention, an inexpensive compound semiconductor substrate can be provided which has an excellent effect of suppressing warpage and cracking and ensures a sufficient breakdown voltage characteristic while maintaining a low resistance value.
    Brief description of the drawings
    Figure 1 is a schematic cross-sectional diagram illustrating one embodiment of a compound semiconductor substrate according to the present invention.
    Figure 2 is a schematic cross-sectional diagram illustrating another embodiment of a compound semiconductor substrate according to the present invention.
    Figure 3 is a schematic cross-sectional diagram illustrating another preferred embodiment of a compound semiconductor substrate according to the present invention.
    Description of the embodiments
    The present invention will be explained below in detail with reference to the accompanying drawings.
    A compound semiconductor substrate Z according to the present invention includes a compound semiconductor layer 3 formed on a main surface of a ground substrate 1 via a seed layer 2, the ground substrate 1 being composed of a sintered body, the starting layer 2 being a single crystal, the compound semiconductor layer 3 has a structure in which a buffer layer 4 and an active layer 5 are sequentially grown on the starting layer 2, the thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less the average thermal expansion coefficient is the entire compound semiconductor layer 3, and an FWHM of the X-ray diffraction peak of the buffer layer 4 is 800arcsec or less.
    Figure 1 is a schematic cross-sectional diagram illustrating one embodiment of the compound semiconductor substrate Z according to the present invention. In the compound semiconductor substrate Z, the start layer 2 and the compound semiconductor layer 3 are formed sequentially on a main surface of the base substrate 1, and the compound semiconductor layer 3 includes a structure in which the buffer layer 4 and the active layer 5 are stacked in this order. Figure 1 is otherwise in
    Essentially, a conceptual diagram and the actual dimensional relationships of the respective layers are different.
    In the present invention, the base substrate 1 is a sintered body. In the prior art, a single crystal has been suitably used in the base substrate, but the reason for this is that the compound semiconductor layer formed on the base substrate takes on the crystallinity of the single crystal to obtain the crystallinity in the plane required as a semiconductor element.
    From this background, it is not necessary that the other portions of the base substrate 1 are necessarily a single crystal as long as only the vicinity of a main surface on which the compound semiconductor layer is formed is a single crystal.
    In the present invention, therefore, a sintered body is used in the base substrate 1, and only the vicinity of the one main surface of the base substrate 1 is provided with the starting layer consisting of a single crystal, so that the compound semiconductor layer 3 can take the crystallinity of the single crystal. In the present invention, therefore, the starting layer 2 guarantees that the region of the single crystal ensures the crystallinity of the compound semiconductor layer 3 and the base substrate 1 is made of a sintered body. When compared with the same materials, a sintered body substrate is superior to a single crystal substrate at first in terms of a lower price and easier production into a large size substrate.
    Moreover, a sintered body has a greater degree of freedom in selecting the material as compared with a single crystal, and a material having a smaller difference in thermal expansion coefficient from the compound semiconductor layer may be suitably used. Moreover, the effect of less warpage of the entire substrate is better than in the case of using a single crystal material in the base substrate.
    Further, the base substrate 1 consisting of a sintered body is advantageous in that the bonding strength is easier to ensure when the base substrate 1 is bonded to the starting layer 2 consisting of a single crystal as compared with the case of connecting single crystal substrates to each other.
    As for the material for the sintered body used as the base substrate 1, known materials used as a semiconductor can be widely applied. The production process thereof is further not particularly limited. Examples of the material may include silicon nitride (Si 3 N 4), aluminum nitride (AlN), silicon carbide (SiC) and boron nitride (BN). Moreover, the substrate 1 does not necessarily have a homogeneous single composition, but the composition or the impurity concentration may be partially different in the substrate 1. Incidentally, in the case of using a sintered body of AlN in the base substrate 1, the presence of yttrium aluminum garnet (YAG) in AlN of 0.5 to 5 wt% is preferable because the thermal conductivity of the base substrate 1 is improved.
    It is not necessary that the base substrate 1 is a complete sintered body, and this may be a composite substrate having a single crystal layer or a plurality of sintered body layers in the middle or on the back surface of the base substrate 1, but a shape that only becomes composed of a sintered body having a single composition is preferable when priority is given to providing homogeneous properties as the compound semiconductor substrate Z.
    The starting layer 2 is next formed on a main surface of the base substrate 1. This start layer 2 is made of a single crystal, and has the role of growth start of the compound semiconductor layer 3 formed thereon. In the present invention, it is intended to obtain a compound semiconductor layer of high quality by providing a starting layer consisting of a single crystal, assuming that it is practically difficult to consider a highly crystalline single crystal layer on a sintered body surface.
    In this starting layer 2, it is not necessary that the other regions are all single crystals, as long as at least a part of the region in contact with the
    Compound semiconductor layer 3 is a single crystal, and the start layer 2 may be a plurality of
    Have multilayer structures in which a related part is polycrystalline or amorphous. However, a mold consisting of only a single crystal having a single composition is more preferable if priority is given to the homogeneous properties of the compound semiconductor substrate Z.
    As a specific example of the starting layer 2, a bulk Si single crystal formed by the CZ method or the FZ method or a Si layer formed on a bulk single crystal by a CVD method is suitable. Although a single crystal of SiC, gallium nitride (GaN) or sapphire may be used, Si is more suitable for the various materials described above in terms of cost and ease of processing.
    The thickness of the start layer 2 is set in a timely manner depending on the selection of the respective materials for the base substrate 1, the start layer 2, and the compound semiconductor layer 3, as well as the characteristics required of the compound semiconductor substrate Z.
    The thickness of the starting layer 2 is preferably 0.05 μτη or more at a minimum against the background of ensuring a thickness required for the crystal growth of the compound semiconductor layer 3, but is preferably 2 μπι or less, since the starting layer 2 itself delays the Compound semiconductor substrate Z can cause if it is too thick. The thickness is preferably from 0.1 to Ιμια.
    The compound semiconductor layer 3 has a structure in which the buffer layer 4 and the active layer 5 are sequentially grown on the starting layer 2. As explained above, the compound semiconductor layer 3 is one which is grown on the start layer 2 having a single crystal surface to ensure crystallinity.
    The compound semiconductor substrate Z may be other components with an insulating film, an electrode, a passivation film, and the like, or may have a recess structure, via structure, or the like as long as it includes a structure in which the buffer layer 4 and the active layer Layer 5 are sequentially stacked.
    The layer structure, thickness, doping concentration,
    Band gap (energy difference) and the like of the active layer 5 can be set in time depending on the required specification.
    The active layer 5 may further be one containing a layer from which desired properties are obtained as electrons move. Examples of the layer may be a light emitting layer in the case of a light emitting diode and an electron passage layer in the case of a field effect transistor, such as a high electron mobility transistor (HEMT), and may also be applied to another type of radio frequency device.
    In the present invention, the thermal expansion coefficient of the sintered body used in the base substrate 1 is 0.7 times or more and 1.4 times or less the average thermal one
    Expansion coefficient of the compound semiconductor layer 3. The warpage of the entire compound semiconductor substrate Z can be reduced when the thermal expansion coefficient in this region is set. For the average thermal
    Expansion coefficients of the compound semiconductor layer 3, a value obtained by dividing the respective thermal expansion coefficients of the buffer layer 4, the active layer 5 and other layers additionally provided with the thickness of each layer in the total thickness of the layer can be used Compound semiconductor layer 3 are provided, and by summing up the resulting values.
    By setting the thermal expansion coefficient of the sintered body as 0.7 times or more and 1.4 times or less the average thermal expansion coefficient of the compound semiconductor layer 3, warpage of the compound semiconductor substrate Z can be sufficiently reduced, for example, compared with the case of application of Si for the base substrate 1.
    A distortion of the entire compound semiconductor substrate Z is also by the ratio of the thickness of the
    Compound semiconductor layer 3 to the thickness of the base substrate 1 is affected, however, in the present invention, it is not required that the thickness of these is particularly severely limited, since the thickness of the base substrate 1 is much thicker than that of the compound semiconductor layer 3.
    For example, if the base substrate 1 is an AlN sintered body and the compound semiconductor layer 3 is GaN, the thickness of the base substrate 1 may be 300 μπι or more in the case where the thickness of the compound semiconductor layer 3 is 7 μπι or more and 15 μη or is less and in particular 7 μη or more and 12 μη or less. However, the upper limit is preferably 1200μη or less, because there are disadvantages in that the treatment property deteriorates, the materials to be used in the gas phase growth device are limited, and the like, although the warpage reduction effect is saturated when the base substrate 1 is too thick.
    Further, the FWHM of the X-ray diffraction peak of the buffer layer 4 according to the present invention is 800 arcsec or less. That is, it is possible to effectively improve the electrical properties of the compound semiconductor layer formed on the buffer layer 4 when the crystallinity of the buffer layer 4 is in a certain preferred level or higher.
    The FWHM of the X-ray diffraction peak is used in the present invention as an indicator for determining the suitability of the crystallinity. As a method of measuring the FWHM, a known method used in the evaluation of the semiconductor crystal is used.
    Incidentally, the FWHM has different values depending on the target crystal orientation, and is also selected in due time when it is necessary to use the value of crystal orientation, but at least possible in the present invention is the electrical properties of the compound semiconductor layer. formed on the buffer layer 4 to significantly improve when the crystallinity is 800 arcsec or less than an absolute value.
    The structure of the buffer layer 4 is not particularly limited, and a known stacked compound semiconductor structure can be widely used. In the prior art, dislocation or warpage is controlled by the use of a multi-layered laminate as a buffer layer, however, in the present invention, it is possible to form the buffer layer 4 having a blocking point for securing crystallinity because the buffer layer 4 is not responsible for the above-explained effect due to the presence of the base substrate 1 and the starting layer 2.
    Thus, it can be said that a layer structure that is simpler and likely to provide higher crystallinity, for example, a single layer of a single material or a multi-layer laminate having a layer number of less than ten layers is more preferable.
    The starting layer 2 has a function of ensuring the crystal orientation and crystallinity of the buffer layer 4, but in the present invention, it also has a function for more effectively relaxing a strain caused by the difference in thermal expansion coefficient between the base substrate 1 and the compound semiconductor layer 3 is caused. Incidentally, the above-explained effect is more suitably applied by optimizing each layer thickness, taking into consideration the thermal expansion coefficient or lattice constant of the base substrate 1, the start layer 2, and the compound semiconductor layer 3.
    In the compound semiconductor substrate Z of the present invention, the film thickness is
    Compound semiconductor layer 3 preferably 7 μm or more and 15 μm or less. In the present invention, an active layer 5 of high quality can be obtained by providing the base substrate 1 and the buffer layer 4. The breakdown voltage characteristic in the longitudinal direction can be sufficiently ensured, and the electrical properties of the active layer 5 are synergistically improved, regardless of the type of compound semiconductor, by setting the layer thickness of the compound semiconductor layer 3 to 7 μιη or more.
    On the other hand, the breakdown voltage characteristic can be improved if the thickness of the
    Compound semiconductor layer 3 is thicker, but the layer thickness is limited to 15 pm or less. The reason is that this is a setting below
    Considering the practical breakdown voltage, and the deterioration of properties other than the breakdown voltage is also taken into account.
    Moreover, in the compound semiconductor substrate Z of the present invention, the active layer 5 is substantially one in which an electron supply layer 5b is formed on an electron passage layer 5a, and in this case, it is preferable to provide a spacer layer 11 between the electron passage layer 5a and the electron supply layer 5b.
    The compound semiconductor substrate Z of the present invention can be produced by using a known method. Suitable examples thereof may include organometallic chemical vapor deposition (MOCVD), however, other gas phase growth methods, for example, a hybrid gas phase epitaxial (the HVPE) method or a molecular beam epitaxy (MBE) method may be used. Moreover, these respective growth methods may be suitably used in combination.
    In the following, the present invention will be described in more detail with reference to FIG. 2 using FIG
    Compound semiconductor substrate Z, which is a preferred embodiment of the present embodiment, and wherein the base substrate 1 is AlN, the starting layer 2 is a silicon (Si) single crystal made by the CZ method or the FZ method, the compound semiconductor layer 3 is a gallium-based nitride made by a gas phase growth method, the active layer 5 is one in which the
    Electron supply layer 5b on the
    Electron passage layer 5a is formed, and the FWHM of the GaN (002) and GaN (100) are X-ray diffraction peaks of the buffer layer 4 each 500a csec or less.
    Examples of the compound semiconductor layer 3 consisting of a gallium-based nitride may include a multilayer structure composed of a combination of a layer formed of substantially GaN and at least one of AlGaN or InGaN, and other layers of AlN, InN, and the like consists.
    The sheet resistance of the electron passage layer 5a generally becomes larger when there is a factor that scatters electrons, such as a doping or an effect in its portion. It is therefore preferable that the electron passage layer 5a has a high purity and a high crystalline quality, and it is therefore also preferable that the related sheet resistance is lower.
    In a gallium-based nitride semiconductor film deposited on a Si substrate, the sheet resistance value of the non-doped electron passage layer 5a is preferably about 400 to 450Ω / □. The electrical resistance of the
    Incidentally, electron passage layer 5a is often evaluated by the sheet resistance value, and so is the present invention.
    It is necessary to reduce the FWHM of the buffer layer 4 to have a low sheet resistance value
    To obtain electron transmission layer 5a, however, a layer thickness on the order of microns is required to achieve this FWHM in the case of using a different kind of substrate, and it is necessary to suitably use a voltage control layer in the deposition step to prevent distortion Suppress cracks.
    On the other hand, in the present invention, in order to realize a small FWHM of the buffer layer 4, the voltage control layer can be eliminated or reduced, if possible, and it is possible to increase the thickness of the active layer 5 by a simple structure. by limiting the thermal expansion difference between the base substrate 1 and the compound semiconductor layer 3, particularly by setting the thermal expansion coefficient of the sintered body forming the base substrate 1 to 0.7 times or more and 1.4 times or less to the average thermal expansion coefficients of the entire compound semiconductor layer 3.
    Moreover, when the buffer layer 4, the electron passage layer 5a and the electron supply layer 5b are all gallium-based nitride semiconductors, it is possible to significantly reduce the sheet resistance value of the electron passage layer 5a and suitably have a sheet resistance value of 4 ΩΩ / D or less are obtained by setting both the FWHM of the GaN (002) and GaN (100) of the X-ray diffraction peaks of the buffer layer 4 to 500 or less.
    That is, in the present invention, it has been found that the sheet resistance value of the
    Electron passage layer 5a itself is affected by the properties of the buffer layer 4 present under the electron passage layer 5a, and further by the start layer 2 and the base substrate 1 present under the buffer layer 4, and these are suitably used as a method of Reduction of the sheet resistance value of the electron passage layer 5a defined.
    As shown in Fig. 3, it is further preferable to provide the spacer layer 11 between the electron passage layer 5a and the electron supply layer 5b, since the effect of improved carrier mobility by the spacer layer 11 is enhanced by a decrease in the sheet resistance value of the electron passage layer 5a.
    It is possible to use a known material, composition and thickness for the spacer layer 11. An AlN spacer layer 11 having a thickness of about 0.5 to 2 nm is suitable, for example, for a case where the electron passage layer 5a is GaN and the electron source layer 5b is AlGaN.
    Moreover, as shown in Fig. 3, a bonding layer 10 may be interposed between the base substrate 1 and the starting layer 2. The base substrate 1 and the starting layer 2, which are made of mutually different materials, are connected more stably when there is the bonding layer 10.
    It is possible to use a known technology and material for the bonding layer 10, but in the present invention, a layer of an oxide of the material forming the starting layer 2 is preferred. The oxide has a better adhesion with respect to the material forming the starting layer 2, so that it is suitable as a bonding layer 10.
    It is preferable that an oxide film is formed by directly oxidizing the surface of the starting layer 2 because the starting layer 2 and the bonding layer 10 are originally strongly bonded to each other, and therefore, the problem that the layer is reduced in the process of grinding is subtracted from the substrate.
    Further, the back surface of the base substrate 1 may be subjected to a high-gloss polishing, and the surface other than the region where the starting layer 2 is formed may be covered with a protective film such as an oxide film.
    Incidentally, the HEMT structure has hitherto been described as an example, however, the compound semiconductor substrate Z according to the present invention may also be applied as a light-emitting diode other than the HEMT structure as long as it has a semiconductor substrate in which a reduction in resistance of the active layer contributes to the improvement of properties.
    The compound semiconductor substrate Z according to the present invention, as explained above, enables the improvement of properties of the active layer which could not be easily achieved in the prior art by a relatively simple configuration.
    The present invention becomes effective even in a compound semiconductor substrate having a diameter of 6 inches or more, particularly in view of the fact that it is particularly difficult to control the warpage of the entire substrate in an extension of the prior art
    Compound semiconductor substrate for HEMT is produced, which has a diameter of 6 inches or more or more and a thickness of the compound semiconductor layer 3 of 7 μπι or more. Moreover, in a compound semiconductor substrate having a diameter of 8 inches, it is possible to provide a compound semiconductor substrate comprising an electron transmission layer having a plane of distortion and a low resistance, which is formed by the prior art technique which is not a single crystal in the base substrate 1 and the starting layer 2 used, can not be achieved.
    Examples
    The present invention will be explained below with particular reference to Example, however, the present invention is not limited to the following examples.
    Example 1: Preparation of Sample 1
    Preparation of the base substrate 1
    A substrate consisting of an AlN sintered body having a diameter of 6 inches and a thickness of 1000 μη was prepared, and this was used as the base substrate 1. Both surfaces of this base substrate were subjected to high gloss polishing to have an average arithmetic roughness Ra = 50 nm or less.
    Preparation for producing the starting layer 2
    A Si single crystal substrate having a diameter of 6 inches, a thickness of 675 μη, a planar orientation (111) and a resistivity of 0.002 Ω-cm was prepared, one surface thereof being one
    Was subjected to high gloss polishing to have an average arithmetic roughness Ra = 50nm or less, and this was subsequently subjected to an oxidation treatment for two hours at 1000 ° C in a 100% oxygen atmosphere using a semiconductor heat treatment furnace to become the substrate thus obtained used as the basis of the starting layer 2.
    Connecting and Processing the Base Substrate 1 and the Base of Start Layer 2
    The mirror-polished surfaces of the base substrate 1 and the base of the starting layer 2, which were prepared as described above, were bonded together by heat compression by a known method, and the base of the starting layer 2 was then surface-polished until it had a thickness of 0.5 μτη, and finally mirror polished with an average arithmetic roughness of Ra = 50 nm or less, to obtain the
    To use the result for the starting layer 2, whereby a connected body of the base substrate 1 and the starting layer 2 was obtained.
    Formation of compound semiconductor layer 3, 1:
    initial layer
    The bonded body was wet cleaned by a known substrate wet cleaning method, then placed in an MOCVD apparatus and subjected to a heat treatment for 15 minutes at 100 ° C in a 100% hydrogen atmosphere, after the temperature was raised. A first initial layer consisting of an AlN single crystal of 100 nm thick was subsequently subjected to gas phase growth at 100 ° C using trimethylaluminum (TMA) and ammonia (NH 3) as sources. The
    Reference growth temperature was set at 100 ° C, and accurate adjustment in a range of 1 to 15 ° C was added in the formation of all subsequent gallium-based nitride semiconductor layers. A second initial layer consisting of an AlxGai_xN single crystal layer (x = 0.1) having a thickness of 100 nm was grown on the initial layer using trimethylgallium (TMG), TMA and NH3 as gas sources.
    Formation of the compound semiconductor layer 3, 2: Formation of the buffer layer
    Next, a GaN single crystal layer having a carbon concentration of 1 × 10 16 atoms / cm 3 and a thickness of 4800 nm and a GaN single crystal layer having a carbon concentration of 5 × 10 19 atoms / cm 3 and a
    Thickness of 3600 nm was subsequently stacked on the second initial layer, and this was used as the buffer layer 4.
    Forming the compound semiconductor layer 3, 3: Formation of the electron passage layer and electron supply layer
    Subsequently, a GaN single crystal layer having a carbon concentration of 1 × 10 16 atoms / cm 3 and a thickness of 700 nm was stacked thereon in the same manner as the electron passage layer 5 a, and an Aly Ga 1-y N single crystal layer (y = 0.25) was further coated 20 nm thick thereon in the same manner as the electron supply layer 5b. Incidentally, the control of the thickness or carbon concentration of each layer formed by gas phase growth was carried out by adjusting the flow rate and supply time of the gas source, the substrate temperature, and other known growth conditions. A sample prepared in this manner was used as Sample 1.
    A sample obtained by depositing up to the buffer layer 4 but without forming the electron passage layer 5a and the electron supply layer 5b was separately prepared, and this was used as a sample 1x.
    Example 2: Preparation of Sample 2
    The entire process was the same as that in Example 1, except that the step of producing the buffer layer 4 in Example 1 was replaced by the step of forming the buffer layer 4 having a multilayer structure in which an AlN single crystal layer with a carbon concentration of 5 x 1019 atoms / cm3 and a thickness of 5nm and a GaN single crystal layer having a carbon concentration of 5 x 1019 atoms / cm3 and a thickness of 30nm were alternately grown to have eight layers each, then a GaN was grown. Single crystal layer having a carbon concentration of 5 x 1019 atoms / cm3 and a thickness of 812 0 nm stacked thereon in the same manner. A sample prepared in this manner was used as Sample 2.
    A sample obtained by depositing to the buffer layer 4 was separately prepared, and this was used as Sample 2X.
    Comparative Example 1: Preparation of Sample 3
    The entire process was the same as that in Example 2, except that the Si single crystal substrate used in the preparation of the starting layer 2 was used as such instead of the base substrate 1 and the starting layer 2 in Example 2. A Sample prepared in this manner was used as Sample 3.
    A sample obtained by depositing to the buffer layer 4 was separately prepared, and this was used as Sample 3X.
    Comparative Example 2: Preparation of Sample 4
    The Si single crystal substrate used in the preparation of the starting layer 2 was used as such instead of the base substrate 1 and the starting layer 2. In the step of producing the buffer layer 4, an AlN single crystal layer having a carbon concentration of 5 × 1019 atoms / cm3 and a thickness of 5nm and a GaN single crystal layer having a carbon concentration of 5 x 1019 atoms / cm3 and a thickness of 30nm were alternately grown to form each of eight layers, then, as step A, a GaN single crystal layer of 2250 nm and the AlN single crystal layer having a thickness of 5 nm and the GaN single crystal layer having a thickness of 30 nm (both each having a carbon concentration of 5 × 10 19 atoms / cm 3) were grown again to have eight layers each. This step A was repeated three times. A GaN single crystal layer having a carbon concentration of 5 × 10 19 atoms / cm 3 and a thickness of 1300 nm was stacked thereon in the same manner, thereby forming the buffer layer 4 having a multilayer structure. The entire process after the formation of the electron passage layer 5a was the same as in Example 1. A sample prepared in this manner was used as Sample 4.
    A sample obtained by depositing to the buffer layer 4 was separately prepared, and this was used as Sample 4X.
    evaluation
    Samples 1 to 4 prepared in Examples 1 and 2 and Comparative Examples 1 and 2 were evaluated for the warpage of the entire compound semiconductor substrate Z, the crystallinity of the buffer layer 4, and the sheet resistance value of the electron passage layer 5a subjected. The warpage was determined by the difference between the maximum value and the minimum value of the distance at which the substrate surface in the main surface center was offset in the substrate thickness direction using a commercially available laser distance meter. The crystallinity was determined by the FWHM of the rocking curve of the (002) and (100) plane peaks respectively obtained by X-ray diffraction using the samples lx to 4X. The sheet resistance was measured at a point in the center of the surface of Samples 1 to 4 using a Hall effect measuring device.
    The default size in the sample 1 was 30 μπι, the default size in sample was 10 μπι and the default size in Comparative Example 4 was 50 μπι. In the samples 1, 2 and 4, no cracking of the film occurred and there was no problem in the shape and appearance of the substrate when the appearance of the substrate was not observed within 3mm from the periphery, but cracking of the film occurred entire surface in Sample 3, so that the evaluation could not be performed. The results for sheet resistance evaluation were moreover as follows. The sheet resistance was 220Q / D in sample 1, 380Q / D in sample 2 and 450Q / D in sample 4.
    In samples lx to 4X, moreover, the FWHM of GaN (002) and GaN (100) was 250 arcsec and 300 arcsec in sample lx, and 400arcsec and 800arcsec in sample 2X, and 550csec and 100o acc in sample 4X, respectively. As explained above, cracking occurred in the film over the entire surface in Sample 3X, so that the evaluation could not be performed.
    As explained above, in the embodiment of the present invention, Samples 1 and 2 have lower sheet resistance compared to Sample 4 in which a sintered body was not used as a base substrate. In particular, the sheet resistance of the electron-supply layer in Sample 1 is reduced by 40 to 45% as compared with that in Sample 4 in which a nitride semiconductor layer is formed on a Si single-crystal substrate of the prior art.
    The delay of both Samples 1 and 2 is also at a practically acceptable level. That is, this indicates that the warpage of the thickness samples 1 and 2 in which the thickness of the compound semiconductor layer is from 7 to 10 μη is in a level from that of the sample 4 in which the thickness of the compound semiconductor layer is from 4 to 5 μιη , and it can therefore be said that the warp reduction effect, which is one of the features of the present invention, is confirmed.
    权利要求:
    Claims (12)
    [1]
    claims
    A compound semiconductor substrate, comprising: a compound semiconductor layer formed on a main surface of a base substrate via a start layer, wherein the base substrate is formed of a sintered body, the start layer is formed of a single crystal, the compound semiconductor layer has a structure having a buffer layer and a base layer active layer which is sequentially grown on the starting layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less at an average thermal expansion coefficient of the entire compound semiconductor layer, and a FWHM of an X-ray diffraction peak of the buffer Layer is 800 arcsec or less.
    [2]
    2. compound semiconductor substrate according to claim 1, wherein a layer thickness of the compound semiconductor layer 7 μιη or more and 15 μπι or less.
    [3]
    The compound semiconductor substrate according to claim 1, wherein the active layer has been obtained by forming an electron supply layer on an electron passage layer.
    [4]
    The compound semiconductor substrate according to claim 2, wherein the active layer has been obtained by forming an electron supply layer on an electron passage layer.
    [5]
    The compound semiconductor substrate according to claim 3, wherein a spacer layer is further provided between the electron passage layer and the electron supply layer.
    [6]
    The compound semiconductor substrate according to claim 4, wherein a spacer layer is further provided between the electron passage layer and the electron supply layer.
    [7]
    The compound semiconductor substrate according to claim 1, wherein the base substrate is an aluminum nitride (A1N) sintered body, the starting layer is a silicon (Si) single crystal obtained by the Czochralski (CZ) method or the floating zone (FZ) method The compound semiconductor is a gallium-based nitride made by a gas-phase growth method, and the FWHM of GaN (002) and GaN (100) are X-ray diffraction peaks of the buffer layer, respectively, 500 arcsec or less.
    [8]
    The compound semiconductor substrate according to claim 2, wherein the base substrate is an aluminum nitride (A1N) sintered body, the starting layer is a silicon (Si) single crystal produced by the Czochralski (CZ) method or the floating zone (FZ) method The compound semiconductor is a gallium-based nitride made by a gas-phase growth method, and the FWHM of GAN (002) and GaN (100) are X-ray diffraction peaks of the buffer layer, each 500 arcsec or less.
    [9]
    The compound semiconductor substrate according to claim 3, wherein the base substrate is an aluminum nitride (A1N) sintered body, the starting layer is a silicon (Si) single crystal produced by the Czochralski (CZ) method or the floating zone (FZ) method That is, the compound semiconductor is a gallium-based nitride produced by a gas phase growth method, and the FWHM of GaN (002) and GaN (100) are X-ray diffraction peaks of the buffer layer each 500 arcsec or less.
    [10]
    The compound semiconductor substrate according to claim 4, wherein the base substrate is an aluminum nitride (A1N) sintered body, the starting layer is a silicon (Si) single crystal produced by the Czochralski (CZ) method or the floating zone (FZ). A method wherein the compound semiconductor is a gallium-based nitride prepared by a gas-phase growth method, and the FWHM of GaN (002) and GaN (100) are X-ray diffraction peaks of the buffer layer each 500 arcsec or less.
    [11]
    The compound semiconductor substrate according to claim 5, wherein the base substrate is an aluminum nitride (A1N) sintered body, the starting layer is a silicon (Si) single crystal produced by the Czochralski (CZ) method or the floating zone (FZ). A method wherein the compound semiconductor is a gallium-based nitride prepared by a gas-phase growth method, and the FWHM of GaN (002) and GaN (100) are X-ray diffraction peaks of the buffer layer each 500 arcsec or less.
    [12]
    The compound semiconductor substrate according to claim 6, wherein the base substrate is an aluminum nitride (A1N) sintered body, the starting layer is a silicon (Si) single crystal produced by the Czochralski (CZ) method or the floating zone (FZ). A method wherein the compound semiconductor is a gallium-based nitride prepared by a gas-phase growth method, and the FWHM of GaN (002) and GaN (100) are X-ray diffraction peaks of the buffer layer each 500 arcsec or less.
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    同族专利:
    公开号 | 公开日
    JP6465785B2|2019-02-06|
    JP2017076687A|2017-04-20|
    US20170110414A1|2017-04-20|
    BE1023890A1|2017-09-05|
    US10068858B2|2018-09-04|
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    法律状态:
    2017-12-13| FG| Patent granted|Effective date: 20170906 |
    优先权:
    申请号 | 申请日 | 专利标题
    JP2015202862A|JP6465785B2|2015-10-14|2015-10-14|Compound semiconductor substrate|
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